If, instead of variables, we wanted to swap signals, we would write:. Let us look at a second example in which we assume that the print subprogram prints the decimal representation of its parameter.
If a is an integer variable and its current value is 15, executing:. If we execute this step by step in a debugger we can see the value of a changing from the initial 15 to 30, 25 and finally 5. If we execute this step by step in a debugger we will not see any value change of s until after the wait instruction. Moreover, the final value of s will not be 15, 30, 25 or 5 but 3! This apparently strange behavior is due the fundamentally parallel nature of digital hardware, as we will see in the following sections.
A VHDL program is a collection of sequential programs that run in parallel. These sequential programs are called processes:. The processes, just like the hardware they are modelling, never end: they are infinite loops.
After executing the last instruction, the execution continues with the first. As with any programming language that supports one form or another of parallelism, a scheduler is responsible for deciding which process to execute and when during a VHDL simulation.
Moreover, the language offers specific constructs for inter-process communication and synchronization. The scheduler maintains a list of all processes and, for each of them, records its current state which can be running , run-able or suspended.
There is at most one process in running state: the one that is currently executed. As long as the currently running process does not execute a wait instruction, it continues running and prevents any other process from being executed.
The VHDL scheduler is not preemptive: it is each process responsibility to suspend itself and let other processes run. This is one of the problems that VHDL beginners frequently encounter: the free running process. Note: variable a is declared locally while signals s and r are declared elsewhere, at a higher level. VHDL variables are local to the process that declares them and cannot be seen by other processes.
Another process could also declare a variable named a , it would not be the same variable as the one of process P3. As soon as the scheduler will resume the P3 process, the simulation will get stuck, the simulation current time will not progress anymore and the only way to stop this will be to kill or interrupt the simulation.
The reason is that P3 has not wait statement and will thus stay in running state forever, looping over its 3 instructions. No other process will ever be given a chance to run, even if it is run-able. Let us assume that our VHDL program does not contain such pathological processes. When the running process executes a wait instruction, it is immediately suspended and the scheduler puts it in the suspended state. The wait instruction also carries the condition for the process to become run-able again.
This condition is recorded by the scheduler. The scheduler then selects another process among the run-able , puts it in running state and executes it. And the same repeats until all run-able processes have been executed and suspended. Important note: when several processes are run-able , the VHDL standard does not specify how the scheduler shall select which one to run.
These so called unconstrained arrays can not be used as signals, however, i. Process Statements include a set of sequential statements that assign values to signals.
These statements allow you to perform step-by-step computations. Process Statements that describe purely combinational behavior can also be used to create combinational logic. The initial value of a variable can be assigned by a globally static expression.
The expression must reference a value of the same type as the variable itself. A procedure is a type of subprogram in VHDL which can help us avoid repeating code. Sometimes the need arises to perform identical operations several places throughout the design. Blogs New entries New comments Blog list Search blogs.
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Differences: variables : They are local; no delay; declared within process signals : They are global before begin ; delay due to wire; declared before key word begin.
NguyenT 5 3 3 bronze badges. Piedone Piedone 2, 1 1 gold badge 20 20 silver badges 42 42 bronze badges. Shared Variables- are like variables but they can be accessed from different processes. Instead they may only be used with protected types. Protected types do not allow assignment.
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